libnds: registers_alt.h ソースファイル

00001 /*---------------------------------------------------------------------------------
00002 
00003         Copyright (C) 2005
00004                 Michael Noland (joat)
00005                 Jason Rogers (dovoto)
00006                 Dave Murphy (WinterMute)
00007                 Chris Double (doublec)
00008 
00009         This software is provided 'as-is', without any express or implied
00010         warranty.  In no event will the authors be held liable for any
00011         damages arising from the use of this software.
00012 
00013         Permission is granted to anyone to use this software for any
00014         purpose, including commercial applications, and to alter it and
00015         redistribute it freely, subject to the following restrictions:
00016 
00017         1.      The origin of this software must not be misrepresented; you
00018                 must not claim that you wrote the original software. If you use
00019                 this software in a product, an acknowledgment in the product
00020                 documentation would be appreciated but is not required.
00021         2.      Altered source versions must be plainly marked as such, and
00022                 must not be misrepresented as being the original software.
00023         3.      This notice may not be removed or altered from any source
00024                 distribution.
00025 
00026 ---------------------------------------------------------------------------------*/
00027 
00028 /*
00029         This file should be deprecated.
00030         
00031         All hardware register defines should be replaced with REG_ for consistency and namespacing
00032 
00033         http://forum.gbadev.org/viewtopic.php?t=4993
00034 
00035 */
00036 #ifndef NDS_REGISTERS_H
00037 #define NDS_REGISTERS_H
00038 
00039 #warning "header provided for assistance in porting to new register names, do not use for release code"
00040 
00041 
00042 #include <nds/ndstypes.h>
00043 
00044 // math registers
00045 #define DIV_CR                          REG_DIVCNT
00046 
00047 #define DIV_NUMERATOR64         REG_DIV_NUMER
00048 #define DIV_NUMERATOR32         REG_DIV_NUMER_L
00049 
00050 #define DIV_DENOMINATOR64       REG_DIV_DENOM
00051 #define DIV_DENOMINATOR32       REG_DIV_DENOM_L
00052 
00053 #define DIV_RESULT64            REG_DIV_RESULT
00054 #define DIV_RESULT32            REG_DIV_RESULT_L
00055 
00056 #define DIV_REMAINDER64         REG_DIVREM_RESULT
00057 #define DIV_REMAINDER32         REG_DIVREM_RESULT_L
00058 
00059 #define SQRT_CR                         REG_SQRTCNT
00060 
00061 #define SQRT_PARAM64            REG_SQRT_PARAM
00062 #define SQRT_PARAM32            REG_SQRT_PARAM_L
00063 
00064 #define SQRT_RESULT32           REG_SQRT_RESULT
00065 
00066 
00067 // graphics registers
00068 
00069 #define DISPLAY_CR              REG_DISPCNT
00070 
00071 #ifdef ARM9
00072 #define WAIT_CR                 REG_EXMEMCNT
00073 #else
00074 #define WAIT_CR                 REG_EXMEMSTAT
00075 #endif
00076 
00077 #define DISP_SR                 REG_DISPSTAT
00078 #define DISP_Y                  REG_VCOUNT
00079 
00080 #define BG0_CR                  REG_BG0CNT
00081 #define BG1_CR                  REG_BG1CNT
00082 #define BG2_CR                  REG_BG2CNT
00083 #define BG3_CR                  REG_BG3CNT
00084 
00085 #define BG0_X0                  REG_BG0HOFS
00086 #define BG0_Y0                  REG_BG0VOFS
00087 #define BG1_X0                  REG_BG1HOFS
00088 #define BG1_Y0                  REG_BG1VOFS
00089 #define BG2_X0                  REG_BG2HOFS
00090 #define BG2_Y0                  REG_BG2VOFS
00091 #define BG3_X0                  REG_BG3HOFS
00092 #define BG3_Y0                  REG_BG3VOFS
00093 
00094 #define BG2_XDX                 REG_BG2PA
00095 #define BG2_XDY                 REG_BG2PB
00096 #define BG2_YDX                 REG_BG2PC
00097 #define BG2_YDY                 REG_BG2PD
00098 #define BG2_CX                  REG_BG2X
00099 #define BG2_CY                  REG_BG2Y
00100 
00101 #define BG3_XDX                 REG_BG3PA
00102 #define BG3_XDY                 REG_BG3PB
00103 #define BG3_YDX                 REG_BG3PC
00104 #define BG3_YDY                 REG_BG3PD
00105 #define BG3_CX                  REG_BG3X
00106 #define BG3_CY                  REG_BG3Y
00107 
00108 #define REG_WIN0H               (*(vu16*)0x4000040)
00109 #define REG_WIN1H               (*(vu16*)0x4000042)
00110 #define REG_WIN0V               (*(vu16*)0x4000044)
00111 #define REG_WIN1V               (*(vu16*)0x4000046)
00112 #define REG_WININ               (*(vu16*)0x4000048)
00113 #define REG_WINOUT              (*(vu16*)0x400004A)
00114 
00115 
00116 #define MOSAIC_CR               REG_MOSAIC
00117 
00118 #define BLEND_CR                REG_BLDCNT
00119 #define BLEND_AB                REG_BLDALPHA
00120 #define BLEND_Y         REG_BLDY
00121 
00122 #define SUB_BLEND_CR    REG_BLDCNT_SUB
00123 #define SUB_BLEND_AB    REG_BLDALPHA_SUB
00124 #define SUB_BLEND_Y             REG_BLDY_SUB
00125 
00126 
00127 #define SERIAL_CR       REG_SPICNT
00128 #define SERIAL_DATA     REG_SPIDATA
00129 #define SIO_CR          REG_SIOCNT
00130 #define R_CR            REG_RCNT
00131 
00132 #define DISP_CAPTURE    REG_DISPCAPCNT
00133 
00134 #define BRIGHTNESS              REG_MASTER_BRIGHT
00135 #define SUB_BRIGHTNESS  REG_MASTER_BRIGHT_SUB
00136 
00137 /*      secondary screen */
00138 #define SUB_DISPLAY_CR   REG_DISPCNT_SUB
00139 
00140 #define SUB_BG0_CR              REG_BG0CNT_SUB
00141 #define SUB_BG1_CR              REG_BG1CNT_SUB
00142 #define SUB_BG2_CR              REG_BG2CNT_SUB
00143 #define SUB_BG3_CR              REG_BG3CNT_SUB
00144 
00145 #define SUB_BG0_X0              REG_BG0HOFS_SUB
00146 #define SUB_BG0_Y0              REG_BG0VOFS_SUB
00147 #define SUB_BG1_X0              REG_BG1HOFS_SUB
00148 #define SUB_BG1_Y0              REG_BG1VOFS_SUB
00149 #define SUB_BG2_X0              REG_BG2HOFS_SUB
00150 #define SUB_BG2_Y0              REG_BG2VOFS_SUB
00151 #define SUB_BG3_X0              REG_BG3HOFS_SUB
00152 #define SUB_BG3_Y0              REG_BG3VOFS_SUB
00153 
00154 #define SUB_BG2_XDX             REG_BG2PA_SUB
00155 #define SUB_BG2_XDY             REG_BG2PB_SUB
00156 #define SUB_BG2_YDX             REG_BG2PC_SUB
00157 #define SUB_BG2_YDY             REG_BG2PD_SUB
00158 #define SUB_BG2_CX              REG_BG2X_SUB
00159 #define SUB_BG2_CY              REG_BG2Y_SUB
00160 
00161 #define SUB_BG3_XDX             REG_BG3PA_SUB
00162 #define SUB_BG3_XDY             REG_BG3PB_SUB
00163 #define SUB_BG3_YDX             REG_BG3PC_SUB
00164 #define SUB_BG3_YDY             REG_BG3PD_SUB
00165 #define SUB_BG3_CX              REG_BG3X_SUB
00166 #define SUB_BG3_CY              REG_BG3Y_SUB
00167 
00168 #define REG_WIN0H_SUB           (*(vu16*)0x4001040)
00169 #define REG_WIN1H_SUB           (*(vu16*)0x4001042)
00170 #define REG_WIN0V_SUB           (*(vu16*)0x4001044)
00171 #define REG_WIN1V_SUB           (*(vu16*)0x4001046)
00172 #define REG_WININ_SUB           (*(vu16*)0x4001048)
00173 #define REG_WINOUT_SUB          (*(vu16*)0x400104A)
00174 
00175 #define SUB_MOSAIC_CR           REG_MOSAIC_SUB
00176 
00177 #define REG_BLDMOD_SUB  (*(vu16*)0x4001050)
00178 #define REG_COLV_SUB    (*(vu16*)0x4001052)
00179 #define REG_COLY_SUB    (*(vu16*)0x4001054)
00180 
00181 /*common*/
00182 
00183 #define REG_DMA0SAD             (*(vu32*)0x40000B0)
00184 #define REG_DMA0SAD_L   (*(vu16*)0x40000B0)
00185 #define REG_DMA0SAD_H   (*(vu16*)0x40000B2)
00186 #define REG_DMA0DAD             (*(vu32*)0x40000B4)
00187 #define REG_DMA0DAD_L   (*(vu16*)0x40000B4)
00188 #define REG_DMA0DAD_H   (*(vu16*)0x40000B6)
00189 #define REG_DMA0CNT             (*(vu32*)0x40000B8)
00190 #define REG_DMA0CNT_L   (*(vu16*)0x40000B8)
00191 #define REG_DMA0CNT_H   (*(vu16*)0x40000BA)
00192 
00193 #define REG_DMA1SAD             (*(vu32*)0x40000BC)
00194 #define REG_DMA1SAD_L   (*(vu16*)0x40000BC)
00195 #define REG_DMA1SAD_H   (*(vu16*)0x40000BE)
00196 #define REG_DMA1DAD             (*(vu32*)0x40000C0)
00197 #define REG_DMA1DAD_L   (*(vu16*)0x40000C0)
00198 #define REG_DMA1DAD_H   (*(vu16*)0x40000C2)
00199 #define REG_DMA1CNT             (*(vu32*)0x40000C4)
00200 #define REG_DMA1CNT_L   (*(vu16*)0x40000C4)
00201 #define REG_DMA1CNT_H   (*(vu16*)0x40000C6)
00202 
00203 #define REG_DMA2SAD             (*(vu32*)0x40000C8)
00204 #define REG_DMA2SAD_L   (*(vu16*)0x40000C8)
00205 #define REG_DMA2SAD_H   (*(vu16*)0x40000CA)
00206 #define REG_DMA2DAD             (*(vu32*)0x40000CC)
00207 #define REG_DMA2DAD_L   (*(vu16*)0x40000CC)
00208 #define REG_DMA2DAD_H   (*(vu16*)0x40000CE)
00209 #define REG_DMA2CNT             (*(vu32*)0x40000D0)
00210 #define REG_DMA2CNT_L   (*(vu16*)0x40000D0)
00211 #define REG_DMA2CNT_H   (*(vu16*)0x40000D2)
00212 
00213 #define REG_DMA3SAD             (*(vu32*)0x40000D4)
00214 #define REG_DMA3SAD_L   (*(vu16*)0x40000D4)
00215 #define REG_DMA3SAD_H   (*(vu16*)0x40000D6)
00216 #define REG_DMA3DAD             (*(vu32*)0x40000D8)
00217 #define REG_DMA3DAD_L   (*(vu16*)0x40000D8)
00218 #define REG_DMA3DAD_H   (*(vu16*)0x40000DA)
00219 #define REG_DMA3CNT             (*(vu32*)0x40000DC)
00220 #define REG_DMA3CNT_L   (*(vu16*)0x40000DC)
00221 #define REG_DMA3CNT_H   (*(vu16*)0x40000DE)
00222 
00223 #define REG_TIME                ( (vu16*)0x4000100)
00224 #define REG_TM0D                (*(vu16*)0x4000100)
00225 #define REG_TM0CNT              (*(vu16*)0x4000102)
00226 #define REG_TM1D                (*(vu16*)0x4000106)
00227 #define REG_TM2D                (*(vu16*)0x4000108)
00228 #define REG_TM2CNT              (*(vu16*)0x400010A)
00229 #define REG_TM3D                (*(vu16*)0x400010C)
00230 #define REG_TM3CNT              (*(vu16*)0x400010E)
00231 
00232 
00233 #define REG_SIOCNT              (*(vu16*)0x4000128)
00234 #define REG_SIOMLT_SEND (*(vu16*)0x400012A)
00235 
00236 #define KEYS            REG_KEYINPUT
00237 #define KEYS_CR         REG_KEYCNT
00238 //??? (sio defines, no link port though)
00239 #define REG_RCNT                (*(vu16*)0x4000134)
00240 #define REG_HS_CTRL             (*(vu16*)0x4000140)
00241 
00242 /* Interupt     enable registers */
00243 #define IE                      REG_IE
00244 #define IF                      REG_IF
00245 #define IME                     REG_IME
00246 
00247 /*controls power  0x30f is all on */
00248 #define POWER_CR        REG_POWERCNT
00249 
00250 /* ram  controllers     0x8     is enabled,     other bits have to do with mapping */
00251 #define REG_VRAM_A_CR   (*(vu8*) 0x4000240)
00252 #define REG_VRAM_B_CR   (*(vu8*) 0x4000241)
00253 #define REG_VRAM_C_CR   (*(vu8*) 0x4000242)
00254 #define REG_VRAM_D_CR   (*(vu8*) 0x4000243)
00255 #define REG_VRAM_E_CR   (*(vu8*) 0x4000244)
00256 #define REG_VRAM_F_CR   (*(vu8*) 0x4000245)
00257 #define REG_VRAM_G_CR   (*(vu8*) 0x4000246)
00258 #define REG_VRAM_H_CR   (*(vu8*) 0x4000248)
00259 #define REG_VRAM_I_CR   (*(vu8*) 0x4000249)
00260 #define REG_WRAM_CNT    (*(vu8*) 0x4000247)
00261 
00262 
00263 
00264 
00265 /*3D graphics suff*/
00266 #define REG_GFX_FIFO            (*(vu32*) 0x4000400)
00267 #define REG_GFX_STATUS          (*(vu32*) 0x4000600)
00268 #define REG_GFX_CONTROL         (*(vu16*) 0x4000060)
00269 #define REG_COLOR                       (*(vu32*) 0x4000480)
00270 #define REG_VERTEX16            (*(vu32*) 0x400048C)
00271 #define REG_TEXT_COORD          (*(vu32*) 0x4000488)
00272 #define REG_TEXT_FORMAT         (*(vu32*) 0x40004A8)
00273 
00274 
00275 #define REG_CLEAR_COLOR         (*(vu32*) 0x4000350)
00276 #define REG_CLEAR_DEPTH         (*(vu16*) 0x4000354)
00277 
00278 #define REG_LIGHT_VECTOR        (*(vu32*) 0x40004C8)
00279 #define REG_LIGHT_COLOR         (*(vu32*) 0x40004CC)
00280 #define REG_NORMAL                      (*(vu32*) 0x4000484)
00281 
00282 #define REG_DIFFUSE_AMBIENT             (*(vu32*) 0x40004C0)
00283 #define REG_SPECULAR_EMISSION   (*(vu32*) 0x40004C4)
00284 #define REG_SHININESS                   (*(vu32*) 0x40004D0)
00285 
00286 #define REG_POLY_FORMAT         (*(vu32*) 0x40004A4)
00287 
00288 #define REG_GFX_BEGIN           (*(vu32*) 0x4000500)
00289 #define REG_GFX_END                     (*(vu32*) 0x4000504)
00290 #define REG_GFX_FLUSH           (*(vu32*) 0x4000540)
00291 #define REG_GFX_VIEWPORT        (*(vu32*) 0x4000580)
00292 
00293 #define REG_MTX_CONTROL         (*(vu32*) 0x4000440)
00294 #define REG_MTX_PUSH            (*(vu32*) 0x4000444)
00295 #define REG_MTX_POP                     (*(vu32*) 0x4000448)
00296 #define REG_MTX_SCALE           (*(vint32*) 0x400046C)
00297 #define REG_MTX_TRANSLATE       (*(vint32*) 0x4000470)
00298 #define REG_MTX_RESTORE         (*(vu32*) 0x4000450)
00299 #define REG_MTX_STORE           (*(vu32*) 0x400044C)
00300 #define REG_MTX_IDENTITY        (*(vu32*) 0x4000454)
00301 #define REG_MTX_LOAD4x4         (*(volatile     f32*) 0x4000458)
00302 #define REG_MTX_LOAD4x3         (*(volatile     f32*) 0x400045C)
00303 #define REG_MTX_MULT4x4         (*(volatile     f32*) 0x4000460)
00304 #define REG_MTX_MULT4x3         (*(volatile     f32*) 0x4000464)
00305 #define REG_MTX_MULT3x3         (*(volatile     f32*) 0x4000468)
00306 
00307 // Card bus
00308 
00309 #define REG_CARD_CR1            (*(vu32*)0x040001A0)
00310 #define REG_CARD_CR1H           (*(vu8*)0x040001A1)
00311 #define REG_CARD_CR2            (*(vu32*)0x040001A4)
00312 #define REG_CARD_COMMAND        ((vu8*)0x040001A8)
00313 
00314 #define REG_CARD_DATA           (*(vu32*)0x04100000)
00315 #define REG_CARD_DATA_RD        (*(vu32*)0x04100010)
00316 
00317 #define REG_CARD_1B0            (*(vu32*)0x040001B0)
00318 #define REG_CARD_1B4            (*(vu32*)0x040001B4)
00319 #define REG_CARD_1B8            (*(vu16*)0x040001B8)
00320 #define REG_CARD_1BA            (*(vu16*)0x040001BA)
00321 
00322 // sound
00323 
00324 #define SOUND_CR                        REG_SOUNDCNT
00325 #define SOUND_MASTER_VOL        REG_MASTER_VOLUME
00326 
00327 #define SOUND_BIAS                      REG_SOUNDBIAS
00328 
00329 #endif