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00064 #ifndef VIDEO_ARM9_INCLUDE
00065 #define VIDEO_ARM9_INCLUDE
00066
00067
00068 #ifndef ARM9
00069 #error Video is only available on the ARM9
00070 #endif
00071
00072 #include <nds/ndstypes.h>
00073 #include <nds/arm9/sassert.h>
00074
00075 #ifdef __cplusplus
00076 extern "C" {
00077 #endif
00078
00079 extern u16 mosaicShadow;
00080 extern u16 mosaicShadowSub;
00081
00082 #define BG_PALETTE ((u16*)0x05000000)
00083 #define BG_PALETTE_SUB ((u16*)0x05000400)
00085 #define SPRITE_PALETTE ((u16*)0x05000200)
00086 #define SPRITE_PALETTE_SUB ((u16*)0x05000600)
00088 #define BG_GFX ((u16*)0x6000000)
00089 #define BG_GFX_SUB ((u16*)0x6200000)
00090 #define SPRITE_GFX ((u16*)0x6400000)
00091 #define SPRITE_GFX_SUB ((u16*)0x6600000)
00093 #define VRAM_0 ((u16*)0x6000000)
00094 #define VRAM ((u16*)0x6800000)
00097 #define VRAM_A ((u16*)0x6800000)
00098 #define VRAM_B ((u16*)0x6820000)
00099 #define VRAM_C ((u16*)0x6840000)
00100 #define VRAM_D ((u16*)0x6860000)
00101 #define VRAM_E ((u16*)0x6880000)
00102 #define VRAM_F ((u16*)0x6890000)
00103 #define VRAM_G ((u16*)0x6894000)
00104 #define VRAM_H ((u16*)0x6898000)
00105 #define VRAM_I ((u16*)0x68A0000)
00107 #define OAM ((u16*)0x07000000)
00108 #define OAM_SUB ((u16*)0x07000400)
00110 // macro creates a 15 bit color from 3x5 bit components
00111
00112 #define RGB15(r,g,b) ((r)|((g)<<5)|((b)<<10))
00113 #define RGB5(r,g,b) ((r)|((g)<<5)|((b)<<10))
00114 #define RGB8(r,g,b) (((r)>>3)|(((g)>>3)<<5)|(((b)>>3)<<10))
00115
00116 #define ARGB16(a, r, g, b) ( ((a) << 15) | (r)|((g)<<5)|((b)<<10))
00117
00119 #define SCREEN_HEIGHT 192
00120
00121 #define SCREEN_WIDTH 256
00122
00123
00124 #define VRAM_CR (*(vu32*)0x04000240)
00125 #define VRAM_A_CR (*(vu8*)0x04000240)
00126 #define VRAM_B_CR (*(vu8*)0x04000241)
00127 #define VRAM_C_CR (*(vu8*)0x04000242)
00128 #define VRAM_D_CR (*(vu8*)0x04000243)
00129 #define VRAM_E_CR (*(vu8*)0x04000244)
00130 #define VRAM_F_CR (*(vu8*)0x04000245)
00131 #define VRAM_G_CR (*(vu8*)0x04000246)
00132 #define WRAM_CR (*(vu8*)0x04000247)
00133 #define VRAM_H_CR (*(vu8*)0x04000248)
00134 #define VRAM_I_CR (*(vu8*)0x04000249)
00136 #define VRAM_ENABLE (1<<7)
00137
00138 #define VRAM_OFFSET(n) ((n)<<3)
00139
00141 typedef enum {
00142 VRAM_A_LCD = 0,
00143 VRAM_A_MAIN_BG = 1,
00144 VRAM_A_MAIN_BG_0x06000000 = 1 | VRAM_OFFSET(0),
00145 VRAM_A_MAIN_BG_0x06020000 = 1 | VRAM_OFFSET(1),
00146 VRAM_A_MAIN_BG_0x06040000 = 1 | VRAM_OFFSET(2),
00147 VRAM_A_MAIN_BG_0x06060000 = 1 | VRAM_OFFSET(3),
00148 VRAM_A_MAIN_SPRITE = 2,
00149 VRAM_A_MAIN_SPRITE_0x06400000 = 2,
00150 VRAM_A_MAIN_SPRITE_0x06420000 = 2 | VRAM_OFFSET(1),
00151 VRAM_A_TEXTURE = 3,
00152 VRAM_A_TEXTURE_SLOT0 = 3 | VRAM_OFFSET(0),
00153 VRAM_A_TEXTURE_SLOT1 = 3 | VRAM_OFFSET(1),
00154 VRAM_A_TEXTURE_SLOT2 = 3 | VRAM_OFFSET(2),
00155 VRAM_A_TEXTURE_SLOT3 = 3 | VRAM_OFFSET(3)
00156 } VRAM_A_TYPE;
00157
00159 typedef enum {
00160 VRAM_B_LCD = 0,
00161 VRAM_B_MAIN_BG = 1 | VRAM_OFFSET(1),
00162 VRAM_B_MAIN_BG_0x06000000 = 1 | VRAM_OFFSET(0),
00163 VRAM_B_MAIN_BG_0x06020000 = 1 | VRAM_OFFSET(1),
00164 VRAM_B_MAIN_BG_0x06040000 = 1 | VRAM_OFFSET(2),
00165 VRAM_B_MAIN_BG_0x06060000 = 1 | VRAM_OFFSET(3),
00166 VRAM_B_MAIN_SPRITE = 2 | VRAM_OFFSET(1),
00167 VRAM_B_MAIN_SPRITE_0x06400000 = 2,
00168 VRAM_B_MAIN_SPRITE_0x06420000 = 2 | VRAM_OFFSET(1),
00169 VRAM_B_TEXTURE = 3 | VRAM_OFFSET(1),
00170 VRAM_B_TEXTURE_SLOT0 = 3 | VRAM_OFFSET(0),
00171 VRAM_B_TEXTURE_SLOT1 = 3 | VRAM_OFFSET(1),
00172 VRAM_B_TEXTURE_SLOT2 = 3 | VRAM_OFFSET(2),
00173 VRAM_B_TEXTURE_SLOT3 = 3 | VRAM_OFFSET(3)
00174 } VRAM_B_TYPE;
00175
00177 typedef enum {
00178 VRAM_C_LCD = 0,
00179 VRAM_C_MAIN_BG = 1 | VRAM_OFFSET(2),
00180 VRAM_C_MAIN_BG_0x06000000 = 1 | VRAM_OFFSET(0),
00181 VRAM_C_MAIN_BG_0x06020000 = 1 | VRAM_OFFSET(1),
00182 VRAM_C_MAIN_BG_0x06040000 = 1 | VRAM_OFFSET(2),
00183 VRAM_C_MAIN_BG_0x06060000 = 1 | VRAM_OFFSET(3),
00184 VRAM_C_ARM7 = 2,
00185 VRAM_C_ARM7_0x06000000 = 2,
00186 VRAM_C_ARM7_0x06020000 = 2 | VRAM_OFFSET(1),
00187 VRAM_C_SUB_BG = 4,
00188 VRAM_C_SUB_BG_0x06200000 = 4 | VRAM_OFFSET(0),
00189 VRAM_C_TEXTURE = 3 | VRAM_OFFSET(2),
00190 VRAM_C_TEXTURE_SLOT0 = 3 | VRAM_OFFSET(0),
00191 VRAM_C_TEXTURE_SLOT1 = 3 | VRAM_OFFSET(1),
00192 VRAM_C_TEXTURE_SLOT2 = 3 | VRAM_OFFSET(2),
00193 VRAM_C_TEXTURE_SLOT3 = 3 | VRAM_OFFSET(3)
00194 } VRAM_C_TYPE;
00195
00197 typedef enum {
00198 VRAM_D_LCD = 0,
00199 VRAM_D_MAIN_BG = 1 | VRAM_OFFSET(3),
00200 VRAM_D_MAIN_BG_0x06000000 = 1 | VRAM_OFFSET(0),
00201 VRAM_D_MAIN_BG_0x06020000 = 1 | VRAM_OFFSET(1),
00202 VRAM_D_MAIN_BG_0x06040000 = 1 | VRAM_OFFSET(2),
00203 VRAM_D_MAIN_BG_0x06060000 = 1 | VRAM_OFFSET(3),
00204 VRAM_D_ARM7 = 2 | VRAM_OFFSET(1),
00205 VRAM_D_ARM7_0x06000000 = 2,
00206 VRAM_D_ARM7_0x06020000 = 2 | VRAM_OFFSET(1),
00207 VRAM_D_SUB_SPRITE = 4,
00208 VRAM_D_TEXTURE = 3 | VRAM_OFFSET(3),
00209 VRAM_D_TEXTURE_SLOT0 = 3 | VRAM_OFFSET(0),
00210 VRAM_D_TEXTURE_SLOT1 = 3 | VRAM_OFFSET(1),
00211 VRAM_D_TEXTURE_SLOT2 = 3 | VRAM_OFFSET(2),
00212 VRAM_D_TEXTURE_SLOT3 = 3 | VRAM_OFFSET(3)
00213 } VRAM_D_TYPE;
00214
00216 typedef enum {
00217 VRAM_E_LCD = 0,
00218 VRAM_E_MAIN_BG = 1,
00219 VRAM_E_MAIN_SPRITE = 2,
00220 VRAM_E_TEX_PALETTE = 3,
00221 VRAM_E_BG_EXT_PALETTE = 4,
00222 } VRAM_E_TYPE;
00223
00225 typedef enum {
00226 VRAM_F_LCD = 0,
00227 VRAM_F_MAIN_BG = 1,
00228 VRAM_F_MAIN_BG_0x06000000 = 1,
00229 VRAM_F_MAIN_BG_0x06004000 = 1 | VRAM_OFFSET(1),
00230 VRAM_F_MAIN_BG_0x06010000 = 1 | VRAM_OFFSET(2),
00231 VRAM_F_MAIN_BG_0x06014000 = 1 | VRAM_OFFSET(3),
00232 VRAM_F_MAIN_SPRITE = 2,
00233 VRAM_F_MAIN_SPRITE_0x06400000 = 2,
00234 VRAM_F_MAIN_SPRITE_0x06404000 = 2 | VRAM_OFFSET(1),
00235 VRAM_F_MAIN_SPRITE_0x06410000 = 2 | VRAM_OFFSET(2),
00236 VRAM_F_MAIN_SPRITE_0x06414000 = 2 | VRAM_OFFSET(3),
00237 VRAM_F_TEX_PALETTE = 3,
00238 VRAM_F_BG_EXT_PALETTE = 4,
00239 VRAM_F_BG_EXT_PALETTE_SLOT01 = 4 | VRAM_OFFSET(0),
00240 VRAM_F_BG_EXT_PALETTE_SLOT23 = 4 | VRAM_OFFSET(1),
00241 VRAM_F_SPRITE_EXT_PALETTE = 5,
00242 } VRAM_F_TYPE;
00243
00245 typedef enum {
00246 VRAM_G_LCD = 0,
00247 VRAM_G_MAIN_BG = 1,
00248 VRAM_G_MAIN_BG_0x06000000 = 1,
00249 VRAM_G_MAIN_BG_0x06004000 = 1 | VRAM_OFFSET(1),
00250 VRAM_G_MAIN_BG_0x06010000 = 1 | VRAM_OFFSET(2),
00251 VRAM_G_MAIN_BG_0x06014000 = 1 | VRAM_OFFSET(3),
00252 VRAM_G_MAIN_SPRITE = 2,
00253 VRAM_G_MAIN_SPRITE_0x06400000 = 2,
00254 VRAM_G_MAIN_SPRITE_0x06404000 = 2 | VRAM_OFFSET(1),
00255 VRAM_G_MAIN_SPRITE_0x06410000 = 2 | VRAM_OFFSET(2),
00256 VRAM_G_MAIN_SPRITE_0x06414000 = 2 | VRAM_OFFSET(3),
00257 VRAM_G_TEX_PALETTE = 3,
00258 VRAM_G_BG_EXT_PALETTE = 4,
00259 VRAM_G_BG_EXT_PALETTE_SLOT01 = 4 | VRAM_OFFSET(0),
00260 VRAM_G_BG_EXT_PALETTE_SLOT23 = 4 | VRAM_OFFSET(1),
00261 VRAM_G_SPRITE_EXT_PALETTE = 5,
00262 } VRAM_G_TYPE;
00263
00265 typedef enum {
00266 VRAM_H_LCD = 0,
00267 VRAM_H_SUB_BG = 1,
00268 VRAM_H_SUB_BG_EXT_PALETTE = 2,
00269 } VRAM_H_TYPE;
00270
00272 typedef enum {
00273 VRAM_I_LCD = 0,
00274 VRAM_I_SUB_BG_0x06208000 = 1,
00275 VRAM_I_SUB_SPRITE = 2,
00276 VRAM_I_SUB_SPRITE_EXT_PALETTE = 3,
00277 }VRAM_I_TYPE;
00278
00279
00281 typedef u16 _palette[256];
00282
00284 typedef _palette _ext_palette[16];
00285
00287 #define VRAM_E_EXT_PALETTE ((_ext_palette *)VRAM_E)
00288
00290 #define VRAM_F_EXT_PALETTE ((_ext_palette *)VRAM_F)
00291
00293 #define VRAM_G_EXT_PALETTE ((_ext_palette *)VRAM_G)
00294
00296 #define VRAM_H_EXT_PALETTE ((_ext_palette *)VRAM_H)
00297
00299 #define VRAM_F_EXT_SPR_PALETTE ((_palette *)VRAM_F)
00300
00302 #define VRAM_G_EXT_SPR_PALETTE ((_palette *)VRAM_G)
00303
00305 #define VRAM_I_EXT_SPR_PALETTE ((_palette *)VRAM_I)
00306
00307
00315 u32 vramSetMainBanks(VRAM_A_TYPE a, VRAM_B_TYPE b, VRAM_C_TYPE c, VRAM_D_TYPE d);
00316
00320 void vramRestoreMainBanks(u32 vramTemp);
00321
00322 static inline
00326 void vramSetBankA(VRAM_A_TYPE a) { VRAM_A_CR = VRAM_ENABLE | a; }
00327
00328 static inline
00332 void vramSetBankB(VRAM_B_TYPE b) { VRAM_B_CR = VRAM_ENABLE | b; }
00333
00334 static inline
00338 void vramSetBankC(VRAM_C_TYPE c) { VRAM_C_CR = VRAM_ENABLE | c; }
00339
00340 static inline
00344 void vramSetBankD(VRAM_D_TYPE d) { VRAM_D_CR = VRAM_ENABLE | d; }
00345
00346 static inline
00350 void vramSetBankE(VRAM_E_TYPE e) { VRAM_E_CR = VRAM_ENABLE | e; }
00351
00352 static inline
00356 void vramSetBankF(VRAM_F_TYPE f) { VRAM_F_CR = VRAM_ENABLE | f; }
00357
00358 static inline
00362 void vramSetBankG(VRAM_G_TYPE g) { VRAM_G_CR = VRAM_ENABLE | g; }
00363
00364 static inline
00368 void vramSetBankH(VRAM_H_TYPE h) { VRAM_H_CR = VRAM_ENABLE | h; }
00369
00370 static inline
00374 void vramSetBankI(VRAM_I_TYPE i) { VRAM_I_CR = VRAM_ENABLE | i; }
00375
00376
00397 #define REG_DISPCNT (*(vu32*)0x04000000)
00398 #define REG_DISPCNT_SUB (*(vu32*)0x04001000)
00399
00400 #define ENABLE_3D (1<<3)
00401 #define DISPLAY_ENABLE_SHIFT 8
00402 #define DISPLAY_BG0_ACTIVE (1 << 8)
00403 #define DISPLAY_BG1_ACTIVE (1 << 9)
00404 #define DISPLAY_BG2_ACTIVE (1 << 10)
00405 #define DISPLAY_BG3_ACTIVE (1 << 11)
00406 #define DISPLAY_SPR_ACTIVE (1 << 12)
00407 #define DISPLAY_WIN0_ON (1 << 13)
00408 #define DISPLAY_WIN1_ON (1 << 14)
00409 #define DISPLAY_SPR_WIN_ON (1 << 15)
00410
00440 typedef enum
00441 {
00442 MODE_0_2D = 0x10000,
00443 MODE_1_2D = 0x10001,
00444 MODE_2_2D = 0x10002,
00445 MODE_3_2D = 0x10003,
00446 MODE_4_2D = 0x10004,
00447 MODE_5_2D = 0x10005,
00448 MODE_6_2D = 0x10006,
00449 MODE_0_3D = (0x10000 | DISPLAY_BG0_ACTIVE | ENABLE_3D),
00450 MODE_1_3D = (0x10001 | DISPLAY_BG0_ACTIVE | ENABLE_3D),
00451 MODE_2_3D = (0x10002 | DISPLAY_BG0_ACTIVE | ENABLE_3D),
00452 MODE_3_3D = (0x10003 | DISPLAY_BG0_ACTIVE | ENABLE_3D),
00453 MODE_4_3D = (0x10004 | DISPLAY_BG0_ACTIVE | ENABLE_3D),
00454 MODE_5_3D = (0x10005 | DISPLAY_BG0_ACTIVE | ENABLE_3D),
00455 MODE_6_3D = (0x10006 | DISPLAY_BG0_ACTIVE | ENABLE_3D),
00457 MODE_FIFO = (3<<16),
00459 MODE_FB0 = (0x00020000),
00460 MODE_FB1 = (0x00060000),
00461 MODE_FB2 = (0x000A0000),
00462 MODE_FB3 = (0x000E0000)
00464 }VideoMode;
00465
00466
00467
00468 #define DISPLAY_SPR_HBLANK (1 << 23)
00469
00470 #define DISPLAY_SPR_1D_LAYOUT (1 << 4)
00471
00472 #define DISPLAY_SPR_1D (1 << 4)
00473 #define DISPLAY_SPR_2D (0 << 4)
00474 #define DISPLAY_SPR_1D_BMP (4 << 4)
00475 #define DISPLAY_SPR_2D_BMP_128 (0 << 4)
00476 #define DISPLAY_SPR_2D_BMP_256 (2 << 4)
00477
00478
00479 #define DISPLAY_SPR_1D_SIZE_32 (0 << 20)
00480 #define DISPLAY_SPR_1D_SIZE_64 (1 << 20)
00481 #define DISPLAY_SPR_1D_SIZE_128 (2 << 20)
00482 #define DISPLAY_SPR_1D_SIZE_256 (3 << 20)
00483 #define DISPLAY_SPR_1D_BMP_SIZE_128 (0 << 22)
00484 #define DISPLAY_SPR_1D_BMP_SIZE_256 (1 << 22)
00485
00486
00487 #define DISPLAY_SPRITE_ATTR_MASK ((7 << 4) | (7 << 20) | (1 << 31))
00488
00489 #define DISPLAY_SPR_EXT_PALETTE (1 << 31)
00490 #define DISPLAY_BG_EXT_PALETTE (1 << 30)
00491
00492 #define DISPLAY_SCREEN_OFF (1 << 7)
00493
00494
00495
00496
00497 #define DISPLAY_CHAR_BASE(n) (((n)&7)<<24)
00498
00499
00500
00501
00502 #define DISPLAY_SCREEN_BASE(n) (((n)&7)<<27)
00503
00504 static inline
00508 void videoSetMode( u32 mode) { REG_DISPCNT = mode; }
00509
00510 static inline
00514 void videoSetModeSub( u32 mode) { REG_DISPCNT_SUB = mode; }
00515
00516 static inline
00520 int videoGetMode() {return (REG_DISPCNT & 0x30007);}
00521
00522 static inline
00526 int videoGetModeSub() {return (REG_DISPCNT_SUB & 0x30007);}
00527
00528 static inline
00532 bool video3DEnabled() {return (REG_DISPCNT & ENABLE_3D) ? true : false;}
00533
00534 static inline
00538 void videoBgEnable(int number) {REG_DISPCNT |= 1 << (DISPLAY_ENABLE_SHIFT + number);}
00539
00540 static inline
00544 void videoBgEnableSub(int number) {REG_DISPCNT_SUB |= 1 << (DISPLAY_ENABLE_SHIFT + number);}
00545
00546 static inline
00550 void videoBgDisable(int number) {REG_DISPCNT &= ~(1 << (DISPLAY_ENABLE_SHIFT + number));}
00551
00552 static inline
00556 void videoBgDisableSub(int number) {REG_DISPCNT_SUB &= ~(1 << (DISPLAY_ENABLE_SHIFT + number));}
00557
00563 void setBrightness(int screen, int level);
00564
00565 #define REG_MASTER_BRIGHT (*(vu16*)0x0400006C)
00566 #define REG_MASTER_BRIGHT_SUB (*(vu16*)0x0400106C)
00567
00568
00569
00570 #define WIN0_X0 (*(vu8*)0x04000041)
00571 #define WIN0_X1 (*(vu8*)0x04000040)
00572 #define WIN0_Y0 (*(vu8*)0x04000045)
00573 #define WIN0_Y1 (*(vu8*)0x04000044)
00574
00575
00576 #define WIN1_X0 (*(vu8*)0x04000043)
00577 #define WIN1_X1 (*(vu8*)0x04000042)
00578 #define WIN1_Y0 (*(vu8*)0x04000047)
00579 #define WIN1_Y1 (*(vu8*)0x04000046)
00580
00581 #define WIN_IN (*(vu16*)0x04000048)
00582 #define WIN_OUT (*(vu16*)0x0400004A)
00583
00584
00585 #define SUB_WIN0_X0 (*(vu8*)0x04001041)
00586 #define SUB_WIN0_X1 (*(vu8*)0x04001040)
00587 #define SUB_WIN0_Y0 (*(vu8*)0x04001045)
00588 #define SUB_WIN0_Y1 (*(vu8*)0x04001044)
00589
00590
00591 #define SUB_WIN1_X0 (*(vu8*)0x04001043)
00592 #define SUB_WIN1_X1 (*(vu8*)0x04001042)
00593 #define SUB_WIN1_Y0 (*(vu8*)0x04001047)
00594 #define SUB_WIN1_Y1 (*(vu8*)0x04001046)
00595
00596 #define SUB_WIN_IN (*(vu16*)0x04001048)
00597 #define SUB_WIN_OUT (*(vu16*)0x0400104A)
00598
00599 #define REG_MOSAIC (*(vu16*)0x0400004C)
00600 #define REG_MOSAIC_SUB (*(vu16*)0x0400104C)
00601
00602 #define REG_BLDCNT (*(vu16*)0x04000050)
00603 #define REG_BLDY (*(vu16*)0x04000054)
00604 #define REG_BLDALPHA (*(vu16*)0x04000052)
00605
00606 #define REG_BLDCNT_SUB (*(vu16*)0x04001050)
00607 #define REG_BLDALPHA_SUB (*(vu16*)0x04001052)
00608 #define REG_BLDY_SUB (*(vu16*)0x04001054)
00609
00610
00611 #define BLEND_NONE (0<<6)
00612 #define BLEND_ALPHA (1<<6)
00613 #define BLEND_FADE_WHITE (2<<6)
00614 #define BLEND_FADE_BLACK (3<<6)
00615
00616 #define BLEND_SRC_BG0 (1<<0)
00617 #define BLEND_SRC_BG1 (1<<1)
00618 #define BLEND_SRC_BG2 (1<<2)
00619 #define BLEND_SRC_BG3 (1<<3)
00620 #define BLEND_SRC_SPRITE (1<<4)
00621 #define BLEND_SRC_BACKDROP (1<<5)
00622
00623 #define BLEND_DST_BG0 (1<<8)
00624 #define BLEND_DST_BG1 (1<<9)
00625 #define BLEND_DST_BG2 (1<<10)
00626 #define BLEND_DST_BG3 (1<<11)
00627 #define BLEND_DST_SPRITE (1<<12)
00628 #define BLEND_DST_BACKDROP (1<<13)
00629
00630
00631
00632 #define REG_DISPCAPCNT (*(vu32*)0x04000064)
00633 #define REG_DISP_MMEM_FIFO (*(vu32*)0x04000068)
00634
00635 #define DCAP_ENABLE BIT(31)
00636 #define DCAP_MODE(n) (((n) & 3) << 29)
00637 #define DCAP_DST(n) (((n) & 3) << 26)
00638 #define DCAP_SRC(n) (((n) & 3) << 24)
00639 #define DCAP_SIZE(n) (((n) & 3) << 20)
00640 #define DCAP_OFFSET(n) (((n) & 3) << 18)
00641 #define DCAP_BANK(n) (((n) & 3) << 16)
00642 #define DCAP_B(n) (((n) & 0x1F) << 8)
00643 #define DCAP_A(n) (((n) & 0x1F) << 0)
00644
00645
00646
00647
00648 #define GFX_CONTROL (*(vu16*) 0x04000060)
00649
00650 #define GFX_FIFO (*(vu32*) 0x04000400)
00651 #define GFX_STATUS (*(vu32*) 0x04000600)
00652 #define GFX_COLOR (*(vu32*) 0x04000480)
00653
00654 #define GFX_VERTEX10 (*(vu32*) 0x04000490)
00655 #define GFX_VERTEX_XY (*(vu32*) 0x04000494)
00656 #define GFX_VERTEX_XZ (*(vu32*) 0x04000498)
00657 #define GFX_VERTEX_YZ (*(vu32*) 0x0400049C)
00658 #define GFX_VERTEX_DIFF (*(vu32*) 0x040004A0)
00659
00660 #define GFX_VERTEX16 (*(vu32*) 0x0400048C)
00661 #define GFX_TEX_COORD (*(vu32*) 0x04000488)
00662 #define GFX_TEX_FORMAT (*(vu32*) 0x040004A8)
00663 #define GFX_PAL_FORMAT (*(vu32*) 0x040004AC)
00664
00665 #define GFX_CLEAR_COLOR (*(vu32*) 0x04000350)
00666 #define GFX_CLEAR_DEPTH (*(vu16*) 0x04000354)
00667
00668 #define GFX_LIGHT_VECTOR (*(vu32*) 0x040004C8)
00669 #define GFX_LIGHT_COLOR (*(vu32*) 0x040004CC)
00670 #define GFX_NORMAL (*(vu32*) 0x04000484)
00671
00672 #define GFX_DIFFUSE_AMBIENT (*(vu32*) 0x040004C0)
00673 #define GFX_SPECULAR_EMISSION (*(vu32*) 0x040004C4)
00674 #define GFX_SHININESS (*(vu32*) 0x040004D0)
00675
00676 #define GFX_POLY_FORMAT (*(vu32*) 0x040004A4)
00677 #define GFX_ALPHA_TEST (*(vu16*) 0x04000340)
00678
00679 #define GFX_BEGIN (*(vu32*) 0x04000500)
00680 #define GFX_END (*(vu32*) 0x04000504)
00681 #define GFX_FLUSH (*(vu32*) 0x04000540)
00682 #define GFX_VIEWPORT (*(vu32*) 0x04000580)
00683 #define GFX_TOON_TABLE ((vu16*) 0x04000380)
00684 #define GFX_EDGE_TABLE ((vu16*) 0x04000330)
00685 #define GFX_FOG_COLOR (*(vu32*) 0x04000358)
00686 #define GFX_FOG_OFFSET (*(vu32*) 0x0400035C)
00687 #define GFX_FOG_TABLE ((vu8*) 0x04000360)
00688 #define GFX_BOX_TEST (*(vs32*) 0x040005C0)
00689 #define GFX_POS_TEST (*(vu32*) 0x040005C4)
00690 #define GFX_POS_RESULT ((vs32*) 0x04000620)
00691 #define GFX_VEC_TEST (*(vu32*) 0x040005C8)
00692 #define GFX_VEC_RESULT ((vs16*) 0x04000630)
00693
00694 #define GFX_BUSY (GFX_STATUS & BIT(27))
00695
00696 #define GFX_VERTEX_RAM_USAGE (*(u16*) 0x04000606)
00697 #define GFX_POLYGON_RAM_USAGE (*(u16*) 0x04000604)
00698
00699 #define GFX_CUTOFF_DEPTH (*(u16*)0x04000610)
00700
00701
00702
00703 #define MATRIX_CONTROL (*(vu32*)0x04000440)
00704 #define MATRIX_PUSH (*(vu32*)0x04000444)
00705 #define MATRIX_POP (*(vu32*)0x04000448)
00706 #define MATRIX_SCALE (*(vs32*) 0x0400046C)
00707 #define MATRIX_TRANSLATE (*(vs32*) 0x04000470)
00708 #define MATRIX_RESTORE (*(vu32*)0x04000450)
00709 #define MATRIX_STORE (*(vu32*)0x0400044C)
00710 #define MATRIX_IDENTITY (*(vu32*)0x04000454)
00711 #define MATRIX_LOAD4x4 (*(vs32*) 0x04000458)
00712 #define MATRIX_LOAD4x3 (*(vs32*) 0x0400045C)
00713 #define MATRIX_MULT4x4 (*(vs32*) 0x04000460)
00714 #define MATRIX_MULT4x3 (*(vs32*) 0x04000464)
00715 #define MATRIX_MULT3x3 (*(vs32*) 0x04000468)
00716
00717
00718 #define MATRIX_READ_CLIP ((vs32*) (0x04000640))
00719 #define MATRIX_READ_VECTOR ((vs32*) (0x04000680))
00720 #define POINT_RESULT ((vs32*) (0x04000620))
00721 #define VECTOR_RESULT ((vu16*)(0x04000630))
00722
00723 #ifdef __cplusplus
00724 }
00725 #endif
00726
00727 #endif