Main Engine Background registers. [詳細]
マクロ定義 | |
| #define | BACKGROUND (*((bg_attribute *)0x04000008)) |
| Overlay for main screen background attributes. Setting the properties of this struct directly sets background registers. | |
| #define | BG_OFFSET ((bg_scroll *)(0x04000010)) |
| Overlay for main screen background scroll registers. Setting the properties of this struct directly sets background registers. | |
| #define | BG_MAP_RAM(base) ((u16*)(((base)*0x800) + 0x06000000)) |
| A macro which returns a u16* pointer to background map ram (Main Engine). | |
| #define | BG_TILE_RAM(base) ((u16*)(((base)*0x4000) + 0x06000000)) |
| A macro which returns a u16* pointer to background tile ram (Main Engine). | |
| #define | BG_BMP_RAM(base) ((u16*)(((base)*0x4000) + 0x06000000)) |
| A macro which returns a u16* pointer to background graphics memory ram (Main Engine). | |
| #define | CHAR_BASE_BLOCK(n) (((n)*0x4000)+ 0x06000000) |
| A macro which returns a u16* pointer to background tile ram (Main Engine). | |
| #define | SCREEN_BASE_BLOCK(n) (((n)*0x800) + 0x06000000) |
| A macro which returns a u16* pointer to background Map ram (Main Engine). | |
| #define | BGCTRL ( (vu16*)0x4000008) |
| Access to all Main screen background control registers via: BGCTRL[x] GBATEK Reference | |
| #define | REG_BG0CNT (*(vu16*)0x4000008) |
| Background 0 Control register (main engine) GBATEK Reference | |
| #define | REG_BG1CNT (*(vu16*)0x400000A) |
| Background 1 Control register (main engine) GBATEK Reference | |
| #define | REG_BG2CNT (*(vu16*)0x400000C) |
| Background 2 Control register (main engine) GBATEK Reference | |
| #define | REG_BG3CNT (*(vu16*)0x400000E) |
| Background 3 Control register (main engine) GBATEK Reference | |
| #define | REG_BGOFFSETS ( (vu16*)0x4000010) |
| #define | REG_BG0HOFS (*(vu16*)0x4000010) |
| Background 0 horizontal scroll register (main engine). | |
| #define | REG_BG0VOFS (*(vu16*)0x4000012) |
| Background 0 vertical scroll register (main engine). | |
| #define | REG_BG1HOFS (*(vu16*)0x4000014) |
| Background 1 horizontal scroll register (main engine). | |
| #define | REG_BG1VOFS (*(vu16*)0x4000016) |
| Background 1 vertical scroll register (main engine). | |
| #define | REG_BG2HOFS (*(vu16*)0x4000018) |
| Background 2 horizontal scroll register (main engine). | |
| #define | REG_BG2VOFS (*(vu16*)0x400001A) |
| Background 2 vertical scroll register (main engine). | |
| #define | REG_BG3HOFS (*(vu16*)0x400001C) |
| Background 3 horizontal scroll register (main engine). | |
| #define | REG_BG3VOFS (*(vu16*)0x400001E) |
| Background 3 vertical scroll register (main engine). | |
| #define | REG_BG2PA (*(vs16*)0x4000020) |
| Background 2 Affine transform (main engine). | |
| #define | REG_BG2PB (*(vs16*)0x4000022) |
| Background 2 Affine transform (main engine). | |
| #define | REG_BG2PC (*(vs16*)0x4000024) |
| Background 2 Affine transform (main engine). | |
| #define | REG_BG2PD (*(vs16*)0x4000026) |
| Background 2 Affine transform (main engine). | |
| #define | REG_BG2X (*(vs32*)0x4000028) |
| Background 2 Screen Offset (main engine). | |
| #define | REG_BG2Y (*(vs32*)0x400002C) |
| Background 2 Screen Offset (main engine). | |
| #define | REG_BG3PA (*(vs16*)0x4000030) |
| Background 3 Affine transform (main engine). | |
| #define | REG_BG3PB (*(vs16*)0x4000032) |
| Background 3 Affine transform (main engine). | |
| #define | REG_BG3PC (*(vs16*)0x4000034) |
| Background 3 Affine transform (main engine). | |
| #define | REG_BG3PD (*(vs16*)0x4000036) |
| Background 3 Affine transform (main engine). | |
| #define | REG_BG3X (*(vs32*)0x4000038) |
| Background 3 Screen Offset (main engine). | |
| #define | REG_BG3Y (*(vs32*)0x400003C) |
| Background 3 Screen Offset (main engine). | |
Main Engine Background registers.
1.6.3